//测试信号模块
module lvds_top (
    input                           inclk,
    input                           pll_rst,
    input               [9:0]       tx_data,
    input                           rx,
    output                          tx,
    output              [9:0]       rx_data,
    output                          rx_data_en,
    output                          clk_10M,
    output                          pll_locked
);

wire                                clk_100M, clk_400M;
wire                                rst;

assign rst = !pll_locked;

trans_data trans_data_inst (
    .rst                            (rst),
    .clk_10M                        (clk_10M),
    .clk_100M                       (clk_100M),
    .tx_data                        (tx_data),
    .tx_out                         (tx)
);

recv_data recv_data_inst (
    .rst                            (rst),
    .clk_100M                       (clk_100M),
    .clk_400M                       (clk_400M),
    .rx                             (rx),
    .rx_data                        (rx_data),
    .rx_data_en                     (rx_data_en)
);

plltx_rx plltx_rx_inst (
    .areset                         (pll_rst),
    .inclk0                         (inclk),
    .c0                             (clk_10M),
    .c1                             (clk_100M),
    .c2                             (clk_400M),
    .locked                         (pll_locked)
);

endmodule
